The semiconductor industry is continually driven to improve chip performance by further miniaturization of devices by process and integration innovations. Chemical Mechanical Polishing/Planarization (CMP) is a powerful technology as it makes many complex integration schemes at the transistor level possible, thereby increasing chip density. Not surprisingly, there are a multitude of new CMP steps and requirements at the Front End of Line (FEOL) transistor fabrication step. The FEOL material stack typically includes a metal gate and multiple stacks of dielectric materials. The prevalently used dielectric films are Silicon Nitride (SiN), Silicon Oxide (SiO2 or TEOS), Poly-silicon (P—Si), Silicon Carbon Nitride (SiCN), Spin On Carbon (SOC) carbon hard mask, and low-k/ultra-low k (SiCOH, SiOC) dielectric films. With the introduction of high-k metal gate technology at 45 nm and FinFET technology at 22 nm chip production by Intel Corporation, SiN, SiO2, SiCN and P—Si films started being used more profusely, and in a greater number of applications in FEOL. Additionally, in Back End of Line (BEOL) applications, with resistivity of conventional barrier materials (Ta/TaN; Ti/TiN) not scaling down for advanced sub-10 nm manufacturing nodes, semiconductor companies are using dielectrics such as SiN, SiO2, and P—Si for various BEOL material stacks. For both FEOL and BEOL, these dielectric films can be used as an etch stop layer, capping material, spacer material, additional liner, diffusion/passivation barrier, hard mask and/or stop-on layer.